;******************** (C) COPYRIGHT 2021 CHIPAT ********************
; * @file     startup_xs32l010.s
; * @brief    CMSIS Core Device Startup File for
; *          xs32l010 Device
; * @version  V1.0.0
; * @date     18. May 2021
; ******************************************************************************/
;/*
; * Copyright (c) 2023 CHIPAT Limited. All rights reserved.
; */

;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------


;<h> Stack Configuration
;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>

Stack_Size      EQU      0x00000600

                AREA     STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem       SPACE    Stack_Size
__initial_sp


;<h> Heap Configuration
;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>

Heap_Size       EQU      0x00000200

                IF       Heap_Size != 0                      ; Heap is provided
                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE    Heap_Size
__heap_limit
                ENDIF


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA     RESET, DATA, READONLY
                EXPORT   __Vectors
                EXPORT   __Vectors_End
                EXPORT   __Vectors_Size

__Vectors       DCD      __initial_sp                        ;     Top of Stack
                DCD      Reset_Handler                       ;     Reset Handler
                DCD      NMI_Handler                         ; -14 NMI Handler
                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
                DCD      0                                   ; -12 Reserved
                DCD      0                                   ; -11 Reserved
                DCD      0                                   ; -10 Reserved
                DCD      0                                   ; -9  Reserved
                DCD      0                                   ; -8  Reserved
                DCD      0                                   ; -7  Reserved
                DCD      0                                   ; -6  Reserved
                DCD      SVC_Handler                         ; -5  SVCall Handler
                DCD      0                                   ; -4  Reserved
                DCD      0                                   ; -3  Reserved
                DCD      PendSV_Handler                      ; -2  PendSV Handler
                DCD      SysTick_Handler                     ; -1  SysTick Handler

                ; Interrupts
                DCD     GPA_IRQHandler                       ; 0 GPIOA  Handler
                DCD     GPB_IRQHandler                       ; 1 GPIOB  Handler
                DCD     GPC_IRQHandler                       ; 2 GPIOC  Handler  
                DCD     GPD_IRQHandler                       ; 3 GPIOD  Handler
                DCD     FLASH_IRQHandler                     ; 4 FLASH  Handler
                DCD     DMA_Channel1_IRQHandler              ; 5 DMA CH1 Handler
                DCD     USART0_IRQHandler                    ; 6 USART0 Handler
                DCD     USART1_IRQHandler                    ; 7 USART1 Handler
                DCD     LPUART_IRQHandler                    ; 8 LPUART Handler
                DCD     DMA_Channel2_IRQHandler              ; 9 DMA CH2 Handler
                DCD     SPI_IRQHandler                       ; 10 SPI Handler
                DCD     0                                    ; 11 Reserved
                DCD     I2C0_IRQHandler                      ; 12 I2C Handler
                DCD     0                                    ; 13 Reserved
                DCD     TIM4_IRQHandler                      ; 14 TIM4 Handler
                DCD     TIM5_IRQHandler                      ; 15 TIM5 Handler
                DCD     LPTIM_IRQHandler                     ; 16 LPTIM Handler
                DCD     0                                    ; 17 Reserved
                DCD     TIM1_BKP_UP_TRG_COM_IRQHandler       ; 18  TIM1 BKP, UP, TRG, COM Handler
                DCD     TIM2_IRQHandler                      ; 19 TIM2 Handler
                DCD     TIM1_CC_IRQHandler                   ; 20 TIM1 CC Handler
                DCD     PCA_IRQHandler                       ; 21 PCA Handler
                DCD     WWDG_IRQHandler                      ; 22 WWDG Handler
                DCD     0                                    ; 23 Reserved
                DCD     ADC_IRQHandler                       ; 24 ADC Handler
                DCD     LVD_IRQHandler                       ; 25 LVD Handler
                DCD     0                                    ; 26 Reserved
                DCD     0                                    ; 27 Reserved
                DCD     RTC_WKUP_IRQHandler                  ; 28 RTC_WKUP Handler
                DCD     0                                    ; 29 Reserved
                DCD     RTC_ALRAM_IRQHandler                 ; 30 RTC_ALRAM Handler
                DCD     RCC_IRQHandler                       ; 31 RCC Handler
__Vectors_End
__Vectors_Size  EQU      __Vectors_End - __Vectors

;define program entry
                AREA     |.text|, CODE, READONLY

; Reset Handler

Reset_Handler   PROC
                EXPORT   Reset_Handler                  [WEAK]
                IMPORT   SystemInit
                IMPORT   __main

                LDR      R0, =SystemInit
                BLX      R0
                LDR      R0, =__main
                BX       R0
                ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler                     [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler               [WEAK]
                B       .
                ENDP	
SVC_Handler     PROC
                EXPORT  SVC_Handler                     [WEAK]
                B       .
                ENDP				
PendSV_Handler  PROC
                EXPORT  PendSV_Handler                  [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
                EXPORT  SysTick_Handler                 [WEAK]
                B       .
                ENDP

Default_Handler PROC

                EXPORT  GPA_IRQHandler                  [WEAK]
                EXPORT  GPB_IRQHandler                  [WEAK]
                EXPORT  GPC_IRQHandler                  [WEAK]
                EXPORT  GPD_IRQHandler                  [WEAK]
                EXPORT  FLASH_IRQHandler                [WEAK]
				EXPORT	DMA_Channel1_IRQHandler         [WEAK]
                EXPORT  USART0_IRQHandler               [WEAK]
                EXPORT  USART1_IRQHandler               [WEAK]
                EXPORT  LPUART_IRQHandler               [WEAK]
				EXPORT	DMA_Channel2_IRQHandler         [WEAK]
                EXPORT  SPI_IRQHandler                  [WEAK]
				EXPORT	I2C0_IRQHandler                 [WEAK]
                EXPORT  TIM4_IRQHandler                 [WEAK]
                EXPORT  TIM5_IRQHandler                 [WEAK]
                EXPORT  LPTIM_IRQHandler                [WEAK]
                EXPORT  TIM1_BKP_UP_TRG_COM_IRQHandler  [WEAK]
                EXPORT  TIM2_IRQHandler                 [WEAK]
                EXPORT  TIM1_CC_IRQHandler              [WEAK]
                EXPORT  PCA_IRQHandler                  [WEAK]
                EXPORT  WWDG_IRQHandler                 [WEAK]
                EXPORT  ADC_IRQHandler                  [WEAK]
                EXPORT  LVD_IRQHandler                  [WEAK]
                EXPORT  RTC_WKUP_IRQHandler             [WEAK]
                EXPORT  RTC_ALRAM_IRQHandler            [WEAK]
                EXPORT  RCC_IRQHandler                  [WEAK]

GPA_IRQHandler                 
GPB_IRQHandler                  
GPC_IRQHandler                  
GPD_IRQHandler                 
FLASH_IRQHandler 
DMA_Channel1_IRQHandler
USART0_IRQHandler             
USART1_IRQHandler             
LPUART_IRQHandler 
DMA_Channel2_IRQHandler
SPI_IRQHandler 
I2C0_IRQHandler
TIM4_IRQHandler          
TIM5_IRQHandler   
LPTIM_IRQHandler               
TIM1_BKP_UP_TRG_COM_IRQHandler  
TIM2_IRQHandler                 
TIM1_CC_IRQHandler   
PCA_IRQHandler                  
WWDG_IRQHandler              
ADC_IRQHandler                
LVD_IRQHandler                  
RTC_WKUP_IRQHandler              
RTC_ALRAM_IRQHandler              
RCC_IRQHandler
                B       .

                ENDP
                
                ALIGN

;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
                 IF      :DEF:__MICROLIB
                
                 EXPORT  __initial_sp
                 EXPORT  __heap_base
                 EXPORT  __heap_limit
                
                 ELSE
                
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
                 
__user_initial_stackheap

                 LDR     R0, =  Heap_Mem
                 LDR     R1, =(Stack_Mem + Stack_Size)
                 LDR     R2, = (Heap_Mem +  Heap_Size)
                 LDR     R3, = Stack_Mem
                 BX      LR

                 ALIGN

                 ENDIF

                 END
;************************ (C) COPYRIGHT CHIPAT *****END OF FILE*****
